The present invention relates to a technique effectively applied to interconnection technology between a pad electrode on a semiconductor chip in a semiconductor integrated circuit device (semiconductor device or electronic circuit device) and an external device.
Published Japanese translation of a PCT application No. 2004-533711 (Patent Document 1) or U.S. Pat. No. 6,534,863 (Patent Document 2) discloses a technique for bonding a gold wire to a pad comprised of a TaN (bonding layer)/Ta (barrier layer)/Cu (seed layer)/Ni (first electroplated layer)/Au (second electroplated layer), or the like from the lower layer side, instead of an aluminum pad whose surface tends to be easily oxidized, in a semiconductor device with a copper wiring structure.